[Published: Mar. 16, 2023]

Tech Predisappointment that Might Have a Good Point This Time Around

Apple's still running mostly "5nm" process technology across most of its non-wearables product lineup, with a certain fraction of "4nm" SoCs (read: third-run 5nm tech) reserved for iPhone 14 Pro. And yet, most tech observers are already looking ahead to second-generation "3nm" process technology, potentially not showing up in any company's shipping product until around 2024. Why?

There's three quick things to unpack here.

(1) Why did I use quotation marks for "5nm", "3nm", etc.? Just to quickly note that today's something-nanometer lithography seems to be industry marketing - which Overzealous Regulators Around the World™ curiously have yet to call AMD, Intel, Samsung, TSMC and others out on, as far as I can tell. Perhaps those regulators won't get too upset as long as the industry can continue to deliver real generational gains in transistor density, overall performance/capability, and/or lower power consumption - and Apple's own "5nm" SoCs (A14, A15, M1-series and M2-series) certainly deliver on performance per watt.

(2) There's two types of near-term 3nm technology being advertised by TSMC, the current market leader and arguable technology leader in semiconductor logic fabrication:

• the "N3" process, also dubbed "N3B" (as in "N3 Baseline"?) in the tech press for some reason, and

• the "N3E" process, a later, different...um...type?...of 3nm technology which TSMC appears to have accelerated to market...for good reason.

(3) The "N3E Hype Crowd", if you'll excuse the categorization, has a legitimate reason for their second-generation-facing enthusiasm. In large part because they're following the TSMC node with an actual roadmap.

N3/N3B: TSMC's First "High-Volume, Limited Release" Tech in Corporate History?

On-Time...

In December 2019, then-TSMC's senior VP for fab operations, J.K. Wang, reportedly provided an update on its future lithography plans.

Their first-run N5 tech had yet to actually ship in finished products, but TSMC was reportedly confident about volume production by first-half 2020...and it met its timetable, as usual. It also reportedly announced volume production of 3nm sometime in 2022 (some months later, TSMC would clarify its volume production timeframe of "2H 2022", and it also met this timetable (barely), contrary to rumors.

As a further indirect rebuke to certain curious rumors, yield was never an issue - at least, if you believe TSMC's repeated statements that yield was just fine.

Arguably More Than Worthy of "Full Node Stride" Status...

Yes, cadence-driven TSMC's N3 doesn't have the most advanced "gate-all-around" transistor design technology that Samsung and Intel are boasting from their latest (Samsung, "MBCFET") or future (Intel, "RibbonFET") fabs. N3 does, however, claim base benefits of up to 15% higher speeds at iso-power, up to 30% power savings at iso-speed, and ~70% logic-only density gain vs. N5.

Overall, N3's power and perf claims vs. N5 are similar, although more modest, than the 20% iso-power perf/40% iso-speed power savings claimed for N5 tech as compared to N7...but we all know "Moore's Law is (Allegedly) Toast" nowadays. More optimistically, companies are easily able to engineer chips that exceed TSMC's perf delta estimates via refining their chip designs and adding custom silicon blocks (NPUs, encode/decode blocks, etc.) to offload certain tasks from the CPU/GPU at lower power consumption. Using Apple as an example, its A14 Bionic (N5 tech) is around 55% faster at single-core CPU in a typical iPhone (Geekbench 6 basis) when compared against the A12 Bionic (N7 tech).

TSMC 3nm clients like Apple also have access to further optimization tech that simply wasn't available in prior tech nodes. Namely, something TSMC calls "FINFLEX", allowing up to three different types of transistor configurations (max performance, max density/efficiency, or an in-between option) for more precisely tuned silicon blocks within the same SoC. Intriguingly, FINFLEX is claimed to allow clients the all-new ability to design notoriously power-hungry GPUs with a dedicated "2-1 fin" type, combining the theoretical efficiency advantages of max transistors, lower voltage.

Is this all TSMC press release hype? Sure, until proven otherwise (and multi-design-transistors-on-one-SoC tech will likely be offered by Samsung and Intel, to be fair). On the other hand, betting against TSMC's track record is iffy at best.

...But "First-Run" N3 Tech Might Be Too Impractical for Most Companies to Bother With...Save One Enormous Exception

So...what's the problem with TSMC's N3, really? In my exceedingly humble opinion: "Demand".

Part of it might be due to macro uncertainty, but I suspect more of it concerns a common problem of cutting-edge technology. Sometimes, it's simply too complicated for "mass adoption", and most times, accessing cutting-edge technology has very high costs. This time around, TSMC seems to have crossed the invisible lines of "too complex" and "too costly" with N3, and found itself with a brand-new lithography node "that almost nobody wanted".

How so? AnandTech's Anton Shilov cites a tech analyst note from Szeho Ng of China Renaissance claiming that "N3" wafers can have up to 25 EUV (extreme ultraviolet) layers, a large increase from the up-to-14 EUV layers reported for N5 tech, which itself was a huge increase from the up-to-four EUV layers reported for an optimized TSMC "7nm" node. More EUV layers, generally speaking, means increased complexity on top of what is already an expensive, delicate patterning technology.

At some point, TSMC itself seemed to acknowledge that it "overcomplicated" its first-run 3nm. The first clue was the naming for its second-run 3nm tech - "N3E", a departure from second-run 7nm "N7P" (used by the A13 Bionic) and second-run 5nm "N5P" (used by A15 Bionic and M2-series Mac SoCs). There is an "N3P" process in the TSMC pipeline, by the way - but it specifically launches after N3E (more on this later).

The second clue was TSMC pulling ahead N3E technology by at least 2-3 months. AnandTech's diligent attention to N3E's benefits also documents some interesting tradeoffs compared to N3:

• per Szeho Ng of China Renaissance, fewer max EUV layers vs. N3

• slightly better iso-speed power efficiency vs. N3 (up to 34% claimed vs. N5 for N3E)

• slightly better iso-power speed boost vs. N3 (up to 18% claimed vs. N5 for N3E)

• slightly worse scaling for logic transistors plus no scaling for SRAM (basically, system caches), compared against N3 which has a small scaling benefit for SRAM over N5

A more mature 3nm process, lower complexity, lower cost, and better perf/W than N3 at the modest downside of reduced transistor density and no SRAM shrink? Suddenly, you can see why even top-tier tech companies like AMD, NVIDIA, and Qualcomm would be perfectly content waiting an extra year until second-run 3nm is available. But that's not all. Like N7 and N5 before it, N3E probably has a direct migration path to N3P with customer-friendly "design rules compatibility"...something that N3, with its more complex parameters and greater EUV utilization, may well lack.

So what is N3 supposed to be? Is it a large-scale, volume-shipping 3nm tech demo of sorts? Perhaps so, but N3's all-but-certain, exclusive-or-close-to-it customer - Apple Inc., with its world-class Hardware Technologies team - has the resources, design experience, motivation, and sales volumes to bring next-gen 3nm-enabled devices to tens of millions of customers (or more!) as quickly as technology cadences allow. And thanks to Apple's ultra-sized appetite for N3 tech, TSMC fabs will still churn out enormous amounts of N3-fabricated SoCs (read: Hsinchu's Fab 18 will get all the utilization it can handle), even if Apple is the only major customer.

N3E as the True 3nm Inflection Point for the Industry, and what it Could Mean for Apple's "First-Generation" 3nm Chips

For most non-Apple customers, the 3nm era likely begins in 2024, unless Samsung beats/matches Apple to market with some high-profile design wins (which won't include its own Galaxy S23 flagship line, which launched in the usual early-part-of-the-year timeframe with a Qualcomm SoC based on TSMC "4nm" tech).

Rather than try to compete with Apple with an expensive, one-off-ish, N3 technology which is rumored to be oversubscribed anyway (by Apple), most of the industry appears to be "ceding" 3nm tech leadership for this year, before trying to steal the spotlight away next year.

It's only a wild guess and should be given appropriately light weight, but I think Apple furthers its lead over the competition, even if it faces incompatible "design rules" and higher chip rearchitecture burden due to no clear compatibility path from N3(B) to N3E. The reason might be summed up in three words: "Learning by doing". Apple gains all of the benefits of 3nm chip design, product integration, and real-world learnings before most of its competitive set, and around a year before its competitive set even ships their first 3nm-enabled products.

The only real "issue" for Apple (aside from absorbing higher costs per N3-enabled SoC) is that of roadmap. Since N3E may not be "design rules-compatible" with N3, will that impact Apple's timeframe for implementing new IP blocks beyond those already onboard the A15 and A16? It's possible that an N3-based SoC focuses more on fundamental CPU, GPU and NPU gains, with new silicon features (such as a ProRes engine starting with A15 Bionic/iPhone 13 Pro) being saved for the N3E >> N3P portion of Apple's 3nm roadmap.

And since N3E has certain density scaling limitations vs. N3, it might also impact Apple's transistor budgeting (since both the A13 and A15 SoCs had significantly higher transistor counts vs. A12 and A14, respectively).

Overall, though, I think the N3 tech platform (especially FINFLEX, which is available across N3 and N3E) still affords Apple plenty of headroom for meaningful generational deltas over its A15 and A16 chips, while still planning for any potential transistor count ceiling once on the N3E "tech track" (reminder: Apple's SoCs got physically larger on second-run 7nm and 5nm).

Consumers looking to upgrade can choose to be early adopters of the N3-based tech that Apple is all but certain to ship before the end of 2023, or they can wait for the more mature "Rev. B" N3E tech which is due around a year after the first-gen 3nm-powered iPhones, Macs and/or iPads. Given the impressive track record of A-chips and M-chips, either choice is likely to be a solid one.